http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2000200830-A

Outgoing Links

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assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_73ebc284a55d5daf0e209d6186c9e65c
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-762
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-76
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-08
filingDate 1999-01-06-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a9c13b04493db6579b758001f94ec96f
publicationDate 2000-07-18-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2000200830-A
titleOfInvention Method for manufacturing semiconductor device having trench element isolation region
abstract (57) Abstract: Provided is a method of manufacturing a semiconductor device having a trench element isolation region, in which an insulating layer in a trench element isolation region is satisfactorily embedded. A method of manufacturing a semiconductor device having a trench element isolation region according to the present invention includes the steps of: Etching the silicon substrate 10 using the stopper layer 14 formed in a predetermined pattern as a mask to form a trench 16; forming an insulating layer 20 filling the trench 16 over the entire surface; A step of flattening the insulating layer 20 using the stopper layer 14 as a stopper; a step of removing the stopper layer 14; a step of forming a silicon layer 90 over the entire surface; Forming a side wall silicon film 92 covering the side wall; thermally oxidizing the side wall silicon film 92 to form a side wall protection film 94; and etching the protruding portion 22 and the side wall protection film 94 to form a trench isolation. Forming a region 23;
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9982157-B2
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priorityDate 1999-01-06-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 25.