| abstract |
(57) [Problem] To prevent a PLL circuit from locking (erroneous synchronization) to an incorrect phase even when the duty of a data signal is deviated from 100%. An erroneous synchronization phase detection unit (13) sets a data signal (DATA) and a clock signal (10) within a phase range in which erroneous synchronization may occur. The output fixing unit 14 detects whether or not the phase difference of the CLK exists, and if the phase difference exists within the false synchronization phase range, the output fixing unit 14 detects the phase detection signal PH. Fix DT to a fixed value. In this way, even if the duty of the data signal deviates from 100%, only one inclination in the same direction can be made in one cycle. For this reason, the phase at which the average value of the phase difference signal becomes the same value can be made one in one cycle, and the PLL circuit can eliminate erroneous synchronization locked to a phase other than the target phase. |