http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2000091452-A

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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8247
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filingDate 1999-07-15-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d53ba2dba6e845cd4d10355a6b17b994
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publicationDate 2000-03-31-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2000091452-A
titleOfInvention Semiconductor storage device
abstract (57) [Summary] A semiconductor memory device configured so that writing or reading is not erroneously performed on a non-selected memory cell transistor adjacent to a selected memory cell transistor when writing or reading data. The purpose is to provide. SOLUTION: A surface of a substrate 11 adjacent to a buried region 12n formed in a semiconductor substrate 11 is covered with an offset sidewall 15n, under which a channel is hardly expanded and a non-selected non-selected adjacent to a selected memory cell transistor. The leakage current to the memory cell transistor can be limited to a small value, and both sides of the buried region 13n having one non-offset sidewall are offset side wall type buried regions 12n, 12n +. 1 so that leakage current can be limited in any direction.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7087955-B2
priorityDate 1998-07-15-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 23.