http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2000081924-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_80787665b837ed3eb503bbcd27c0043a http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_34263a1d9767236ba10183da556a136b |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-407 |
| filingDate | 1998-09-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f4c5c0081eb3942fc3e3c08ca406f2dc |
| publicationDate | 2000-03-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2000081924-A |
| titleOfInvention | Semiconductor integrated circuit |
| abstract | (57) Abstract: A semiconductor integrated circuit capable of reducing power supply noise and power consumption due to the operation of a clock buffer while reducing clock skew. A semiconductor integrated circuit has a first transmission path transmitting a first clock signal (CLK1) only during a power-on reset period and a second transmission path transmitting a second clock signal (CLK2). It has a plurality of connected clock control circuits (3). The clock control circuit receives the second clock signal and receives the third clock signal (CLK 3) is supplied to the sequential circuit, and a phase variable circuit (30, 31) capable of varying the input / output phase, and detects the phase difference between the first clock signal and the third clock signal and makes the phase difference constant. And a phase difference detection circuit (32) for controlling the phase variable circuit. The control state by the phase detection circuit is determined by using the first clock signal every power-on reset. |
| priorityDate | 1998-09-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 40.