http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2000021997-A

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assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5547f741b25666fc4ae5195cf71a979b
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-092
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-265
filingDate 1998-06-30-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f7b14d042df40dc006f43428e7f790f9
publicationDate 2000-01-21-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2000021997-A
titleOfInvention Semiconductor device and manufacturing method thereof
abstract (57) Abstract: To form a complementary MIS transistor on a semiconductor substrate, a junction capacitance and a photolithography step are reduced. SOLUTION: When a complementary MOS transistor is formed on a P-type semiconductor substrate 1, an N-type impurity is introduced into the entire thickness of the gate electrodes 8 and 9 so that the N-type impurity is deep and deep in the gate electrode 9. The need for ion implantation is eliminated. Therefore, the source and drain regions having the required concentration and depth can be formed in the N-type MOS transistor region, and the junction capacitance can be reduced. Since these N-type impurities have sufficiently low concentrations, the polarity can be easily inverted by implanting P-type impurities at a conventional concentration.
priorityDate 1998-06-30-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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