http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2000020339-A

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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F11-22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F15-78
filingDate 1998-06-29-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_58aa47f8dc6e12ec4dfe505bb5156121
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3513beaaab1876184a39920b26e9b3d2
publicationDate 2000-01-21-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2000020339-A
titleOfInvention Semiconductor integrated circuit device
abstract (57) [PROBLEMS] To realize an interface control circuit capable of efficiently receiving processing request signals of a plurality of blocks synchronously operating according to clock signals of different frequencies, and to realize an emulation unit or the like built in a microcontroller or the like. Increase processing speed and reduce the time required for emulation using the same. On the other hand, a cycle of a clock signal TCLK having a relatively high frequency is coupled to a peripheral bus PB having a cycle of a clock signal PCLK having a relatively high frequency as a substantial bus cycle. In a microcontroller or the like incorporating an emulation unit coupled to a JTAG bus, which is a substantial bus cycle, a processing request signal TREQ output from, for example, a TAP controller on the JTAG bus side is converted to a clock signal TCL. The signal is taken into the latch LTRQ in accordance with the clock signal PCLK directly without being synchronized with K, synchronized, and received.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7506228-B2
priorityDate 1998-06-29-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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