| abstract |
(57) [PROBLEMS] To reduce the size of a memory cell by eliminating the need for a layout margin in contacts between upper and lower wiring layers of an SRAM, and to reduce the wiring capacity of a bit line to enable high-speed operation. SOLUTION: A pair of driving transistors Qd1 and Qd2 are provided. And the transfer transistors Qt1 and Qt2 and the high resistance load R 1, R2, a pair of bit lines BL1, BL2, and VCC. An SRAM is composed of a wiring and a GND wiring. A gate electrode and a word line 107 of each transistor are provided in a first layer, a high resistance load 113 (R1, R2) is provided in a second layer, and a VC is provided. The C wiring 121 and the GND wiring 122 are formed in the third layer, and the bit lines 128 (BL1, BL2) are formed in the fourth layer. The common contact 112 for connecting the high-resistance load 113 to the source / drain region of the transistor does not penetrate other conductive layers, so that a layout margin between the common contact 112 and the other conductive layer becomes unnecessary, and the cell size is reduced. The size can be reduced. |