http://rdf.ncbi.nlm.nih.gov/pubchem/patent/GB-2545264-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_ab054d4fd1810c2c2350c52d00de0add |
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| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-021 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0026 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0097 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0033 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-841 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-826 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-20 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0069 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-004 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0028 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-80 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0007 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-8836 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-067 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-00 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-24 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C13-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L45-00 |
| filingDate | 2015-12-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8966e7c170bc05a04ab75a6e90de8d5b http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_42edecf86094d8dabd5aa3f7af3eb4a5 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d26ea496d31094de87adbb17e664ce8a |
| publicationDate | 2017-06-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | GB-2545264-A |
| titleOfInvention | A storage array |
| abstract | A cross-point memory array comprising correlated electron switching memory elements A memory device comprising a storage array comprising a first signal line 1d-f, a second signal line WO0, WO1 and at least one correlated electron switch in (CES) in electrical communication with both the first and second signal lines, and 14, 18, 22 16 control circuitry to drive the correlated electron switch with at least one programming (write) signal. The first and second signal lines and CES memory elements may form a cross-point array and may correspond to bitlines, and wordlines respectively, and whereby the CES element is located at the cross-point. The programming of the CES element to a first state may comprise setting the first write programming signal set to a first voltage and first current value. A second voltage and current value will determine the second state of the CES memory element. An embodiment to set the respective voltage/current values may comprise NMOSFET 31 and PMOSFET 30 devices connected to Vset supply 18 (see figure 3). The array may further comprise read circuitry 22 (figure 4) which comprises a resistive element 34 is arranged in a resistive ladder in conjunction with the target CES switch, and whereby preferably the resistive element is also a separate correlated electron switch set to the first memory state. Feedback circuitry may also be included in the read circuitry 36, 38 to detect a first or second state of the target CES memory element. Control of parasitic sneak paths may be limited by the use of controlled bias voltages on the respective signal lines, in particular with respect to non targeted CES cells. A method of fabrication and a storage array are also included. |
| priorityDate | 2015-12-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 60.