http://rdf.ncbi.nlm.nih.gov/pubchem/patent/GB-2502662-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0815 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-126 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-123 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0897 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0811 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0817 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0804 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-08 |
| filingDate | 2013-02-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_41f5bfebef414579d669d128671c319d http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ad9fc76f2390687ee28eeab7601a490f http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_98574838c2da15a6e9bcb9219a63a2e5 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e01bbba1e8560b93f9de623d821b298b http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_39eaa7547ceb3ba3092e408568f061d8 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_261bbb7a4883eb2ab36d6ed4a673cec1 |
| publicationDate | 2013-12-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | GB-2502662-A |
| titleOfInvention | Handling of Deallocation Requests in System Having Upper and Lower Level Caches |
| abstract | A deallocate request specifying a target address associated with a target cache line is sent from processor core to lower level cache; if the request hits the replacement order of the lower level cache is updated such that the target is more likely to be evicted (e.g. making the target line least recently used [LRU]) in response to a subsequent cache miss. The replacement order may not be updated with further accesses to target cache line prior to eviction. The lower cache may include load and store pipelines, with deallocation requests sent to the load pipeline. The deallocate instruction may be executed at completion dataset processing, and may be sent to lower level cache regardless of hitting in the upper cache. Lower cache may include state machines servicing data requests, with retaining and updating performed without allocation of state machine/s to the request. A compiler may insert the deallocation instruction into program code executed by the processor core, in response to the detection of an end of dataset processing. An interconnect fabric may couple the processing units. |
| priorityDate | 2012-03-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 29.