| abstract |
The invention prevents information leakage attacks that utilise timeline alignment such as Differential Power Analysis (DPA). Data processing in a CPU is concealed by inserting a random number of instruction fetch cycles during execution of a program and, while the random number of instruction fetch cycles are occurring, mimicking the power consumption associated with fetching instructions from memory, executing the instructions in program sequence, and writing results to memory registers. The mimicking of power consumption is achieved by the inclusion of an additional dummy register 222, an additional AND gate to emulate AND gates 221 associated with conventional registers 221, and a pseudo program counter 232 to emulate the operation of an actual program counter 230. At the conclusion of the random number of instructions, normal program execution recommences by re-fetching the same instructions which were initially fetched but this time updating memory locations in the normal way. The insertion of the random number of instruction fetch cycles is controlled by a Random Instruction Mask (RIM) control flag 202. Other embodiments are disclosed, including a cryptographic bus architecture that prevents usage of side channel information by randomly toggling the polarity of a target bit at a data bus driver. |