| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_51ea83920fa687e50007860670ffd5ef |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3611
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-0208
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3208
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3283
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-2022
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2320-0276 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F17-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3216
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-2081
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F15-80 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F15-80
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G3-36
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G3-32
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F17-16 |
| filingDate |
2006-03-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bba5179590b4288ffc65de49c75cc6ba
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f36708030f39d59ac084d2909a2c637b |
| publicationDate |
2007-09-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
GB-2436377-A |
| titleOfInvention |
Data processing hardware for non-negative matrix factorisation |
| abstract |
The invention relates to data-processing hardware accelerators and related methods for matrix factorisation especially non-negative matrix factorisation (NMF). Embodiments of the invention are particularly useful for driving electroluminescent displays such as OLED displays (figs. 1a, 1b). A matrix factorisation hardware accelerator for factorising an input matrix (Q, fig. 4b) into a pair of matrices (R, C) comprises a first memory 408 storing elements of first factor matrix (R); a second memory 406 storing elements of second factor matrix (C); a grid of processors 402, coupled to the first and second memories to perform a plurality of NMF operations in parallel; and a controller 406 to control writing of input matrix (Q) into grid of processors 402 and to write elements of first and second factor matrices (R,C) into the first and second memory stores. A processor block 402 may also comprise at least one multiply-add unit and a processor memory block. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9311897-B2 |
| priorityDate |
2006-03-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |