| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03B19-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F7-68
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-0814
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-0816
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K5-1565
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K5-00006 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K5-13
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F7-68
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K5-156
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03B19-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-081
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-4076
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-407
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K5-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R25-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K5-00 |
| filingDate |
2003-12-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e108ea9be346576f017f7df657715c2b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2d04ff7cade838bbb3e7efec6b370ded |
| publicationDate |
2004-08-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
GB-2398194-A |
| titleOfInvention |
A clock frequency doubler with high and low output phases of equal length |
| abstract |
A CMOS frequency doubler for use in a synchronous memory comprises a 90 degree delay-locked-loop 210,230 and an XOR gate 220. Phase detector 231 (figure 4) provides in each input cycle a signal V1 which exceeds or is less than the reference voltage V2 in dependence on whether the delay of the delay circuit 210 exceeds 90 degrees. The comparator 232 compares V1 with V2 and controls the up-down counter 233 which outputs a digital code to control the delay circuit 210. The delay circuit may comprise a series connection of logic inverters. The drive strength, and hence the delay, of the inverters may be controlled by selection of a set of parallel-connected inverters (figures 5 and 6). Alternatively, the delay circuit may comprise a set of delay sections subject to selective bypass. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8604831-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/GB-2486003-B
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/GB-2486003-A |
| priorityDate |
2003-02-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |