| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_b1c5f332dddaff914ed798fc54999535 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-2853
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L22-34 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-822
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-26
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-544 |
| filingDate |
2001-06-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b61aa9c538db34fb90fa3b15bd818b0e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_655bd01bb6e1e0c9984c7db29d274538 |
| publicationDate |
2002-05-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
GB-2368974-A |
| titleOfInvention |
Method of testing an integrated circuit by assessing a conductive region formed at the periphery of the substrate |
| abstract |
A method of testing an integrated circuit involves providing substrate (10, Fig. 2) with bond pads (20) and conductive region (30a) connected to two of the bond pads (20), and assessing the conductive region (30a) via the connected bond pads (20). The conductive region (30a) is preferably formed at an outer periphery of the substrate surrounding the bond pads (20), and may have chamfered edges (75, Fig. 4). The conductive region may be tested by assessing an electrical characteristic of the region such as resistance, conductivity, or cross-talk. This assessment of the conductive region (30a) is used to determine the electrical characteristic of the integrated circuit, and to detect failure in the integrated circuit caused by effects such as stress migration. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-10254756-B4
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7888672-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8323991-B2 |
| priorityDate |
2000-06-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |