http://rdf.ncbi.nlm.nih.gov/pubchem/patent/GB-2336241-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_88fc7f9eb617072238851d46591a0c76 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0251 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-02 |
| filingDate | 1998-04-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5104419601b328883b651348319cd1d2 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_aad85a9d308604d4c348d2749892e235 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5f21b402f98375969894736ecf5a931c |
| publicationDate | 1999-10-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | GB-2336241-A |
| titleOfInvention | Substrate-triggering electrostatic discharge protection circuit for deep-submicron integrated circuits |
| abstract | A substrate-triggering electrostatic discharge (ESD) protection circuit is provided for use on a deep-submicron integrated circuit for ESD protection. The ESD protection circuit is incorporated between an input pad IP and the input stage 10 of the internal circuit 40 of an integrated circuit formed on a substrate, and comprises an NMOS transistor N1 and resistor R1 coupled to ground. The substrate of the transistor N1 is coupled to the substrate of a field oxide device (FOD) F1 also connected between the input pad 10 and ground. The FOD F1 includes a lateral parasitic bipolar junction transistor (LBJT) the base of which is formed from the FOD substrate. ESD stress causes snapback breakdown in transistor N1 which generates substrate current which triggers LBJT and turns on FOD F1 to bypass ESD current to ground, so protecting the gate oxide in the input stage. The FOD F1 may be replaced by a second NMOS transistor. A further embodiment includes two PMOS transistors in addition. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/FR-2844929-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7880234-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7203050-B2 |
| priorityDate | 1998-01-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 21.