http://rdf.ncbi.nlm.nih.gov/pubchem/patent/GB-2332779-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10S257-903 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B10-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B10-12 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8244 |
| filingDate | 1998-12-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4d93ec51b0859db641e69d7494c02753 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d34372c1d0c0f136e853e34e8cc20d68 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ab6299fdc043c88569983886ceb81669 |
| publicationDate | 1999-06-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | GB-2332779-A |
| titleOfInvention | CMOS static random access memory device |
| abstract | A static random access memory cell includes first and second transfer transistors Qt1,Qt2 one conductivity e.g. of/n-channel type, first and second driving transistors Qd1,Qd2 of the same conductivity type and first and second load transistors Q11,Q12 of opposite conductivity type. Each of the transistors has source and drain regions on opposite sides of a channel region formed in a semiconductor substrate and a gate over the channel region. The cell has: a first common region defined by the drain regions 28,24 of the first transfer transistor Qt1 and the first driving transistor Qd1 connected in series therethrough; and a second common region defined by the drain regions 36,32 of the second transfer transistor Qt2 and the second driving transistor Qd2 connected in series therethrough. The drain region 40 of the first load transistor Q11 is disposed adjacent the first common region between the first and second common regions. The drain region 44 of the second load transistor Q12 is disposed between the drain region 40 of the first load transistor Q11 and the second common region. First and second gate electrode layers 46,48 are disposed generally parallel to each other, and respectively serve as the gates of the first driving transistor Qd1 and the first load transistor Q11 and as the gates of the second driving transistor Qd2 and the second load transistor Q12. Each of the first and second gate electrode layers 46,48 is formed at a first level; and first and second interconnecting layers 54,56 are formed at a second level different from the first level, the first interconnecting layer 54 connecting the first common region to the drain region of the first load transistor Q11 and the second gate electrode layer, the second interconnecting layer 52 connecting the second common region to the drain region of the second load transistor Q12 and the first gate electrode layer. This arrangement reduces the aspect ratio of the cell. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/FR-2843481-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6879511-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-1388896-A1 |
| priorityDate | 1997-12-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 24.