| abstract |
A digital signal processing system comprising a central processing unit core 2, a memory 8 and a coprocessor 4 operates using coprocessor memory access instructions. The addressing mode information within these coprocessor memory access instructions (P, U, W, Offset) not only controls the addressing mode used by the central processing unit core 2 but is also used by the coprocessor 4 to determine the number of data words in the transfer being specified such that the coprocessor 4 can terminate the transfer at the appropriate time. The Offset field within the instruction may be used to specify changes to be made in the value provided by the central processing unit core 2 upon execution of a particular instruction and also to specify the number of words in the transfer. If the Offset field is not being used, then the number of words to be transferred may default to 1. |