http://rdf.ncbi.nlm.nih.gov/pubchem/patent/GB-2317500-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5d7576285d411d00c697e07270d2814a |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-3011 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4175 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-765 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66863 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-481 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76898 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0649 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28587 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-417 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-765 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-285 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-338 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-48 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06 |
| filingDate | 1996-12-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7f0ab3ef15abbb2856a63b1a8ad394ca |
| publicationDate | 1998-03-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | GB-2317500-A |
| titleOfInvention | Semiconductor device manufacture |
| abstract | A semiconductor device is manufactured by a method comprising: (a) successively forming semiconductor layers 61,62 of opposite conductivity types on a semiconductor substrate 60; (b) forming a semiconductor element in a region 36 of the upper layer 62; (c) forming a first resist pattern (63) covering the region 36; (d) implanting ions into the remaining portion 41 of the layers 61,62, using the first resist pattern (63) as a mask; (e) forming a first wiring layer 45 on the remaining portion 41 and a second wiring layer 46 extending from it to a portion of the semiconductor element; (f) forming a second resist pattern 66 on the reverse side with an aperture opposite the first wiring layer 45; (g) wet etching a hole 42 to the first wiring layer 45; (h) depositing an insulating layer 70, using the second resist pattern 66 as a mask; (I) exposing the first wiring layer 45 by reactive ion etching, using the second resist pattern 66 as a mask; (j) removing the pattern 66; and (k) providing an electrically conductive layer (43) on the exposed area of the first wiring layer 45 and on the insulating layer on the inner wall 421 of the hole 42. Alternatively, steps (h) and (I) may be replaced by: (h') enlarging the aperture in the second resist pattern 66 to the end opening of the hole 42 and (I') depositing an insulating layer on the inner wall 421 of the hole but not on an exposed area of the first wiring layer 45. |
| priorityDate | 1996-03-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 31.