| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_a2bcaf91101a370a3d64e3190366357f |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2225-06541
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10S438-94
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10S438-977
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10S438-975
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76805
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2225-06524 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76898
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0688
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-0657 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-98
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L25-065
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-06 |
| filingDate |
1996-04-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_832db2c321911241b30b08c3ce551a08 |
| publicationDate |
1996-11-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
GB-2300518-A |
| titleOfInvention |
A method of vertical integration for microelectronic systems |
| abstract |
A method of vertical integration for microelectronic systems can be carried out with standard semiconductor technologies compatible with CMOS and makes it possible to reduce the cycle times in manufacture and to increase the yield, compared with known methods. In the method, the individual component layers are processed independently of one another in different substrates (1, 8) and are then joined together. Firstly, vias (7) are opened in the front side of a ready-processed top substrate (1) and penetrate all component layers present. Then a processed bottom substrate (8) is bonded to the top substrate, front face to front face. The top substrate in the substrate stack which now exists is thinned from the rear side, down to the vias (7). Then the opened vias are extended through the remaining layers down to a metallisation plane (11) of the bottom substrate and the electrical contact (15) between the top and bottom substrates is created. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7205204-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7436027-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-1526567-A3 |
| priorityDate |
1995-05-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |