| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6a16b9f3d03f72e59a63285a9d4ca176 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7325
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76885
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L28-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1083
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-8249
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5222
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-7682
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28525
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-8248
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5221 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8249
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-522
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-285
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8248
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-732 |
| filingDate |
1993-09-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9fd77456537808018fddec6bc5c8098c |
| publicationDate |
1994-03-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
GB-2270419-A |
| titleOfInvention |
Interconnect lines for integrated circuits |
| abstract |
In a process for fabricating an integrated circuit (IC) which includes a plurality of devices coupled together by a system of metal interconnects, a method of forming said system above the surface of a semiconductor substrate comprising the steps of: (a) forming a plurality of conductive pedestals (102) on said surface of said substrate, a first portion of said pedestals forming electrical contacts to said devices, said pedestals being formed to a predetermined height such that the top surface of said pedestals is higher than any feature of said substrate; (b) depositing a first layer of polyimide over said substrate to a thickness which is sufficient to cover said pedestals; (c) anisotropically etching said first polyimide layer until the upper surface of said first polyimide layer is roughly coplanar with said top surface of said pedestals; and (d) forming a first set of metal interconnect lines (108) over said first polyimide layer, thereby electrically coupling selected ones of said pedestals. To reduce parasitic capacitance the polyimide layer is etched away to form a system of air-bridge interconnects. <IMAGE> |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-03021676-A2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-03021676-A3 |
| priorityDate |
1990-01-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |