http://rdf.ncbi.nlm.nih.gov/pubchem/patent/GB-2102168-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_12a5fa0b2010a795be2ba1cb12a5619e |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F3-0682 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-24 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G5-227 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G5-222 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F3-0601 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03M11-20 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-24 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F3-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03M11-20 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G5-22 |
| filingDate | 1979-07-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_440cafaeeca2db7f8b3a0e2f41fc94fc |
| publicationDate | 1983-01-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | GB-2102168-A |
| titleOfInvention | Computer |
| abstract | The computer system of this invention has, as the heart of the system, a simple processing unit for providing most data processing by the computer system under control of a read-only memory which contains only instructions and other data for the CPU. The system also includes a random access memory, a keyboard, a video terminal, and a port device in the form of a tape recorder/player. A master clock initiates timing used throughout the system. A multi-line data bus interconnects the CPU and the different memories of the system including the keyboard and the video RAM. Bi-directional communication is possible on the data bus. The addressing of these different memories is by way of an address bus from the CPU, which is a unidirectional bus. Data to be operated upon is basically stored in the random access memory. The keyboard is used for inputting data to the CPU and the video terminal is used for displaying data. Switch 52 (Fig. 14A) is a reset switch which, when manually operated forces the CPU to a known address. <IMAGE> |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/GB-2157033-A |
| priorityDate | 1978-07-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 30.