http://rdf.ncbi.nlm.nih.gov/pubchem/patent/GB-1517181-A

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Predicate Object
assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e9ec95f75bc5dcc8f2c6f36fd3ee1ca6
classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L1-06
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filingDate 1975-06-11-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationDate 1978-07-12-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber GB-1517181-A
titleOfInvention Data receiving apparatus
abstract 1517181 Data receiving apparatus WESTERN ELECTRIC CO Inc 11 June 1975 [17 June 1974] 24950/75 Heading H4L Apparatus for receiving from first and second transmission paths a data word comprising a predetermined number N of bits, includes means for providing for utilisation the complete data word from one of the paths if the difference between N and the number of bits received from the other path is greater than a predetermined value D or, if the difference is equal to or less than D, for providing for utilization both complete data words after reception of the complete word from the other path. As described, identical data is transmitted along two data links A, B (A being 200m longer than B), data arriving via A 1À2 msec later than via B, equivalent to 3 bits in the embodiment described. Here N = 27 bits and D = 6 bits. The receivers for A and B are shown in Figs. 2 and 3. Data is received at modem MA (MB) and entered in shift register DSRA (DSRB) under the control of clock AIA (BIB) which synchronously enters 1's in "counter" registers CAI (CBI). Flip-flop FFA (FFB) detects when a complete word has been received, gate 210 (346) provides a signal PC22A=0 (PC22B=0) when the 22nd bit has been received, and gates 350-377 (301-327) gate the data word out of the register. (1) A-word more than 6 bits behind B- word. LBRFFB = 1 and PC22A = 1 so gate 41, Fig. 4 enabled to provide a signal DWGB which enables gates 301-327 for the complete word in DSRB. (2) A-word within 6 bits of B-word. Now PC22A=0, so gate 41 not enabled. When DSRA contains all 27 bits, LBRFFA = 1 to enable gate 42. Now gate 43 or 44 is enabled according as the second received bit was 1 or 0 (signal OEBIT). A signal GAAM or GBAM causes a differentiator 340 or 328, Figs. 7-8 (not shown) to set a flip-flop 341 or 329 to allow a clock A2A or B2B to read out the contents of DSRA, DSRB for bitwise comparison in an XOR gate 366, Fig. 3. If the two words are identical, FF337 is not set and gates 301-327 or 350-377 are enabled (gates 345. or 339). (3) "UNITARY" mode. Switch 45 provides a signal SMPX which enables gate 46 or 47 when a register contains a complete word, which is then gated out without comparison by means of signal DWGA or DWGB. (4) When the first bit of a succeeding word is received (bit 1 is a 0 which sets a FF 21 or 32) while a current word is in a register, that word is immediately gated out: gate 260 (380) provides a signal FBNWDA (FBNWDB) which, with signal LBRFFA or LBRFFB, enables gate 411 or 49 to provide signal DWGA or DWGB. (5) Discontinuity in transmission: if, e.g. the first bit of the A-word is received before the first bit of the B-word, while the 27th bit of the B-word has been received and the 27th bit of the A-word has not, then the complete received word is immediately gated out. XOR gates 261, 382 detect the presence of the 1st bit and the absence of the 2nd bit (signals PCIA, PCIB) and set FF414 or 415; the outputs from 414, 415 and signals LBRFFA, LBRFFB enable gate 416 or 417 to provide signal DWGA or DWGB.
priorityDate 1974-06-17-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID419520325

Total number of triples: 18.