http://rdf.ncbi.nlm.nih.gov/pubchem/patent/GB-1515179-A
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| filingDate | 1975-10-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 1978-06-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | GB-1515179-A |
| titleOfInvention | Semiconductor devices |
| abstract | 1515179 Semi-conductor devices SONY CORP 23 Oct 1975 [26 Oct 1974] 43656/75 Heading H1K A silicon transistor substrate 1 of N-type semi-conductivity comprises a N-type region of low impurity concentration overlying a N<SP>+</SP> region of high impurity concentration covered by a thernally oxidized silicon dioxide layer 2 for use as a diffusion mask, having opening 3 for base region and annular opening 4 for guard ring region formed by conventional photo-etching. P-type impurities are in diffused to form base 5 and guard ring 6, and a depletion layer is formed adjacent collector junction JC by reverse bias, which extends to guard ring 6 (Fig. 1B). During diffusion silicon dioxide layers are thermally oxidized in openings 3, 4 and an opening 7 is photo-etched in the oxide layer overlying the base. N-type impurities are in diffused to form an emitter region (Fig. 1C). The oxide layer is then etched off (Fig. 1D, not shown) and a passivating layer 9 of polycrystal silicon containing oxygen is superimposed, followed by a passivating layer 10 of polycrystal silicon containing nitrogen; utilizing the apparatus of Fig. 2 (not shown). Then a silicon dioxide layer 11 is formed on a layer 10 as an etch mask, in which openings 12, 13 are formed by photoetching (Fig. IF) with pyrophosphoric acid. Thereafter layers 10, 9 are etched over the mask using fluoric and nitric acids; after which aluminium electrodes are vapour deposited on layer 11 and the exposed base and emitter regions 5, 8, and etched to form a base electrode 14 and emitter electrode 15, while aluminium is vapour deposited on the underface of substrate 1 to form a collector electrode (Fig. 1G); the element then being encapsulated or sealed in a can. The passivating layers 9, 10 are imposed by placing the substrate in a furnace surrounded by a heater, in an atmosphere of monosilane, nitrogen monoxide, and nitrogen (Fig. 2, not shown) to form layer 9 containing oxygen, and adding ammonia and subtracting nitrogen monoxide to form layer 10 containing nitrogen. PN diodes may be prepared similarly (Fig. 3, not shown) and the second passivating layer 10 may be of silicon nitride. N channel and P channel MOSFETS 31, 32 (Fig. 9) may be formed in a common N-type silicon substrate 30. A P-type island 33 is formed in channel 31 and N-type source and drain regions 34, 35 are formed in island 33, with source and drain electrodes 36, 37 of aluminium thereon. Similarly P-type source and drain regions 38, 39 are formed in channel 32 with source and drain electrodes 40, 41. Gate insulant layers 42, 43 of silicon dioxide are imposed on areas between the respective source and drain regions and superimposed thereon are gate electrodes 44, 45. Passivating as above layers 9, 10 are applied to the main surface of substrate 30, and layer 9 covers the exposed part of PN junction J, between region 33 and substrate 30 of channel 31; the exposed parts of junctions JS defining source regions 34, 38, and junctions JD defining drain regions 35, 39 except for the junction parts formed in the gate regions. Passivating layer 10 covers layer 9, and the silicon dioxide layer 11 remains in situ under electrode 37. Drain and source regions 35, 38 and gate electrodes 44, 45 are interconnected to form a complementary inverter circuit. The regions 33, 38, 39 and regions 34, 35 are formed sequentially in the substrate by conventional diffusion over a silicon dioxide mask, subsequently removed for imposition of the passivating layers 9, 10 into which openings are made overlying the gate regions, and insulant gate layers 42, 43 are formed by thermal oxidation. Other openings are made in the passivating layers for the source, drain, and gate electrodes. In a bipolar integrated circuit (Fig. 10) NPN transistors 51, 52 are conventionally formed in a P-type silicon substrate 50 and passivating layers 9, 10 are deposited thereon with silicon dioxide layer 11; so as to cover the exposed parts of reverse biased PN junctions J formed by P<SP>+</SP> regions 53 separating the N-type regions 54, 55, and also the exposed parts of the collector junctions and emitter junctions. Layer 10 may be replaced by alumina or silicone resin coated on the first passivating layer 9, e.g. in a diode (Fig. 11, not shown). The openings of the polycrystalline silicon layers may be formed by plasma-etching over a resistant mask. |
| priorityDate | 1974-10-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
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