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filingDate 1972-11-22-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationDate 1974-07-03-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber GB-1358510-A
titleOfInvention Enhancement-type complementary mis semiconductor device
abstract 1358510 Semi-conductor devices SUWA SEIKOSHA KK 22 Nov 1972 [25 Nov 1971] 53882/72 Heading H1K Complementary IGFETs, both of which exhibit a threshold voltage of not greater than 1.2 volts, are formed in a (100) oriented N-type Si substrate 11 or epitaxial layer having a resistivity greater than 30#/cm., the gate insulations of both IGFETs comprising silicon nitride 20 on silicon oxide 19 and the source, drain and gate metallization 22 being evaporated Al. As shown the P channel device comprises B-doped P-type source and drain regions diffused into the substrate 11 from a boron oxide layer, and the N channel device is formed in a P-type pocket 13 diffused from a B-doped silicon oxide layer. The N-type source and drain regions 18 are diffused from a phosphoric oxide layer. A further silicon oxide layer 21 preferably covers the nitride layer 20 except at the gate region. Care is taken at all stages of the manufacture to exclude contaminants in the gate insulation which would tend to raise the threshold voltage, particularly in the P channel device, and details of the necessary precautions are given. In a modification of the illustrated structure the nitride layer 20 covers the exposed edges of the oxide 19 as well as its top surface.
priorityDate 1971-11-25-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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