http://rdf.ncbi.nlm.nih.gov/pubchem/patent/GB-1312429-A

Outgoing Links

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classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-412
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B10-12
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11
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http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-412
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088
filingDate 1972-03-20-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationDate 1973-04-04-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber GB-1312429-A
titleOfInvention Monolithic memory cell
abstract 1312429 Memory cell array INTERNATIONAL BUSINESS MACHINES CORP 20 March 1972 [14 April 1971] 12861/72 Heading G4C [Also in Division H3] A memory cell of two insulated gate fieldeffect transistors 11, 12 intercoupled drain-togate has two load insulated gate field-effect transistors 22, 23 each with thicker gate-channel insulation then that of the transistors 11, 12. A transistor 31 is parasitic and is formed by a conductor 35<SP>1</SP> (Fig. 2, not shown), passing between doped regions 34 and 30 when the cell is of integrated form. It is maintained off, when transistors 22, 23 are turned on, by voltage on line 30 which increases the threshold of the transistor 31. The cell has bit/sense lines 39, 40 and a plurality of such cells may be formed in one monolithic silicon body (Fig. 3, not shown) to form a memory array.
priorityDate 1971-04-14-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

Incoming Links

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Total number of triples: 18.