| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_99505f5f312672820e9f78c254c00a4d |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02181
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0217
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-022 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31111
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02126
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-84
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1207
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32053
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-324
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02667
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02164
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-8221
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823437
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76254
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76895
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-30604
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-26513 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-76
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-306
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-311 |
| filingDate |
2018-12-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a557cefd7fa9ac72b951c1cae5a90155
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d85d0122acd5e6bcb3530b53ca2693ab |
| publicationDate |
2020-06-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
FR-3091016-A1 |
| titleOfInvention |
3D CIRCUIT WITH MESA INSULATION FOR THE MASS PLAN AREA |
| abstract |
Realization of a level device (N1, N2) of superimposed components comprising in this order: a) providing on a given level (N1) provided with components (T11, T12) produced in a first semiconductor layer (11): a stack comprising a second semiconductor layer (36) capable of accommodating a transistor channel (T21) of level (N2) higher than said given level (N1), said stack comprising a plane layer (34) located between the first layer semiconductor (11) and the second semiconductor layer (36) and an insulating layer (35) separating the ground plane layer (34) from the second semiconductor layer (36), islands being defined in the second semiconductor layer (36), b) form a gate (42) of a transistor (T21) on an island, c) define by etching separate portions in the second semiconductor layer (34) of plane of mass so as to release a space (51) around a first etched portion of the ground plane layer di spotted under and facing said island d) form an insulating zone around said island and said first portion by depositing a layer of insulating material (62) covering the grid (42) and said island, the insulating layer (62) filling said space (51) around said first portion of the ground plane layer. Figure for abstract: 1G. |
| priorityDate |
2018-12-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |