| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_209553962cfc04543cf9de5730e0408c |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76802 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31111
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823475
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-522
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-585
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5283
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-4803
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76816
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-488
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5226
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-03
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-573
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-06 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K1-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-04 |
| filingDate |
2016-11-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8ef4464714ad0f42530f71650b646dcf
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a3ce7e55e104f9896a0914edcbe914ff
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_580184a6bcfda43247b4021db939d6be
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_19b992211b98ab139ff6ef2efb15863c |
| publicationDate |
2018-05-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
FR-3059145-A1 |
| titleOfInvention |
METHOD OF FORMING AT LEAST ONE ELECTRICAL DISCONTINUITY IN AN INTEGRATED CIRCUIT AND CORRESPONDING INTEGRATED CIRCUIT |
| abstract |
An integrated circuit comprising over a semiconductor substrate (SB) a plurality of electrically conductive pads located respectively between integrated circuit component regions and a first metallization stage of the integrated circuit and embedded in an insulating region (RIS2), said plurality of pads having first pads (PLT1) in electrical contact with corresponding first component areas (Z1) and at least one second pad not in electrical contact with a corresponding second component area (Z2), thereby forming least an electrical discontinuity. |
| priorityDate |
2016-11-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |