| abstract |
Method for producing an integrated memory cell with multilayer insulator according to the technology with silicon gates and comprising a contact in overlapping and self-aligning polysilicon. According to this process on a substrate it comprising layers 12, 13 of SiO2 and layers of nitride 14, 24, the gate oxidation 15 of the peripheral transistors is carried out after the deposition of the multiple layers of insulator constituting the memories 13, 14 , 24 and a stop layer 16. Application in particular to the manufacture of integrated MNOS memory cells. |