http://rdf.ncbi.nlm.nih.gov/pubchem/patent/ES-336790-A2
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e9ec95f75bc5dcc8f2c6f36fd3ee1ca6 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10T428-12597 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10T428-12549 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10T428-12812 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10T428-12576 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10T428-12986 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10T428-12681 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N97-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01B1-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C23F1-02 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01B1-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L49-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C23F1-02 |
| filingDate | 1967-01-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 1968-02-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | ES-336790-A2 |
| titleOfInvention | METHOD OF MANUFACTURING A CIRCUIT INTEGRATED BY SELECTIVE CORROSION OF A SUBSTRATE COVERED WITH MULTIPLE LAYERS OF THIN FILM, PERFECTED. |
| abstract | A thin film circuit is made by the selective sequential etching of a laminate 20, Fig. 3, comprising a substrate 21 of glass or ceramics, a resistive layer 22 of tantalum nitride or niobium nitride, a protective layer 23 of Sb, Bi, Mo, W or Zr, and an electrode layer 24 of Ta or Cb the protective layer 23 protects the resistive layer 22 during the etching of the electrode layer 24. Layers 22-24 are deposited by sputtering or vacuum deposition, preferably in a continuous process. In one embodiment, Fig. 5, a first resist 26, is applied by silkscreening or photographically, to a Ta electrode layer 24 in the pattern of a desired conductorcapacitor circuit, and the exposed areas of layer 24 are etched with an etchant such as hot NaOH which does not react with the Sb layer 23. Resist 26 is removed, and the exposed areas of Sb layer 23 are removed by etching as with H 2 SO 4 or aqua regia, which do not attack layers 22, 24. A second resist 27, Fig. 9, is now applied to the conductor-capacitor pattern and also to the areas of layer 22 required for resistor formation, and exposed areas of layer 22 are removed, as with NaOH alternatively, a mixture of HF and HNO 3 may be used, in which case the formation of an oxide layer between substrate 21 and layer 22 is desirable to prevent undercutting, as disclosed in Specification 962,015. Resist 27 is now removed. The values of the resistors are trimmed by anodization, and the Ta layer 24 is anodized to form a dielectric layer 28, Fig. 11, for capacitors, which are completed by the vapour deposition of Au top electrodes 29. Finally, terminals 30 and conductive paths 31 are deposited, being made of Au, or successive layers of Ni-Cr alloy, Cu and Pd. In a modification, a conductive layer for terminals 30 is deposited above layer 24 before the first etching step. In another modification, layers 22, 23 are etched together by a mixture of HF and HNO 3 in a single step. The invention is described with reference to the production of a frequency rejection filter circuit (Fig. 12, not shown) this comprises an inductor which may be formed by thin-film technique or may be a conventional inductor connected to the thin-film circuit. The Specification contains a table of etchants suitable for use when protective layer 23 is formed of Bi, Mo, W or Zr. |
| priorityDate | 1966-02-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 30.