http://rdf.ncbi.nlm.nih.gov/pubchem/patent/ES-2799502-T3
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_8bb531ac161ea927fd276b48f26bc7af |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y02D10-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-3287 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y02D30-50 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-3293 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-3287 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-3293 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-3275 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-324 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-3296 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G05F1-56 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F15-16 |
| filingDate | 2015-10-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2020-12-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c2a09934f3413355f66620b8f8eb5f40 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_25f058fcd7f94f48b7d05d051306637e http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_52b5e8ce76b20245e369c3ff10e45717 |
| publicationDate | 2020-12-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | ES-2799502-T3 |
| titleOfInvention | Fast SMP / ASMP mode switching hardware appliance for a high performance, low power and low cost multi-processor system |
| abstract | A multiprocessor processing system (MP) (100), characterized in that it comprises: a voltage regulator and bypass circuit (280) configured to receive a first supply voltage (VDD) and generate a second supply voltage (VDDb), wherein the second supply voltage has a lower voltage value than the first supply voltage; a first processor (110a) configured to receive and operate in accordance with a first clock signal having a first predetermined frequency and the first supply voltage; a second processor (110b) configured to receive and operate according to either the first clock signal or a second clock signal having a second predetermined frequency, different from the first predetermined frequency and to receive and operate according to the first supply voltage or the second supply voltage; a controller (290) coupled to the voltage regulator and bypass circuit (280) and configured to generate a bypass signal to be sent to said voltage regulator and bypass circuit (280) to selectively input the first supply voltage or the second supply voltage to the second processor; and wherein the first processor (110a) is further configured to receive and operate in accordance with the first clock signal and the first supply voltage during both a first mode and a second mode of operation; wherein said controller (290) comprises a finite state machine (FSM (292)); and if a signal input LDD_MODE_SELECT in said controller (290) is high, then if an SMP / ASMP_SELECT switch command, indicating operation in ASMP mode, is received in controller (290), controller (290) will issue a low BYPASS signal and a high EN signal to said voltage regulator and bypass circuit (280), and based on these values for the EN and BYPASS signals, the FSM (292) transitions to the ASMP mode state ( 320), wherein before entering said ASMP 320 mode state, a Delay2 state (315) is entered by the FSM (292) that provides a predetermined amount of delay time before the FSM (292) output the BYPASS signal low and enter the ASMP (320) mode state, where Delay2 can be any suitable time period interval, depending on the physical operating characteristics of the type of voltage regulator used to generate the second voltage ( VDDb), and if the toggle command indicates ope In the SMP mode, the controller will output a high BYPASS signal and a high EN signal to said voltage regulator and bypass circuit (280) and based on these values for the EN and BYPASS signals, the FSM (292) makes a transition to the SMP mode state (330), wherein prior to entering the SMP mode state (330), a Delay1 state (335) is entered which provides a predetermined amount of delay time before the FSM (292) outputs the BYPASS signal high and enters the SMP mode state (330) where Delay1 can be any suitable time period interval, for example, submicroseconds to tens of microseconds, depending on the operational characteristics Physics of the type of voltage regulator used to generate the first supply voltage (VDD). |
| priorityDate | 2014-10-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 44.