| abstract |
An integration structure (SI) for connecting a plurality of semiconductor devices (DS), is disclosed, the integration structure comprising a substrate (SB), a first face (SIS1) and a second face (SIS2) , the first face (SIS1) being intended to receive the semiconductor devices (DS), the integration structure (SI) comprising, at the level of the first face (SIS1), at least one routing level (1 NR) , the routing level(s) comprising: at least one first conductive routing track (PC) in a conductive material; and at least a first superconducting routing track (PS) in a superconducting material. |