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filingDate 2020-12-11-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9474cc20d5698478d74f3cd06dd3acaf
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publicationDate 2021-09-29-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber EP-3886152-A1
titleOfInvention Stacked transistor structures with asymmetrical terminal interconnects
abstract Integrated circuitry comprising stacked first and second transistor structures. One of a source, drain or gate terminal of an upper-level transistor structure is coupled to one of a source, drain or gate terminal of a lower-level transistor structure through an asymmetrical interconnect (295) having a lateral width that increases within a dimension (y) parallel to a semiconductor sidewall of the upper-level transistor by a greater amount than in an orthogonal dimension (x). A dielectric material (230) between the upper and lower transistor structures may be anisotropically etched asymmetrically by orienting a workpiece to be non-orthogonal to a reactive ion flux. Varying an angle between the reactive ion flux and a plane of the second transistor during an etch of the dielectric material may ensure an etched opening is of sufficient bottom dimension to expose a terminal of the lower-level transistor even if not perfectly aligned with the second transistor structure.
priorityDate 2020-03-27-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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