| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_51d028c578ae85cb937b5b34a5129fbc |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2223-6677 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5226
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76897
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76895
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02175
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76834
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76816 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
| filingDate |
2020-06-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8e8a045aefbbce31b6668eace2521f23
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_46c9af104c379286c7eae829ad82d1ea
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_40732bc43bd5fad129bfe2c5dbfaeb69
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d354b852ff5ddfa4c0cb6e6fc1f50dad
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_abd479e1a7f8574d0cf755cf5ed0e85e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ffb241c34178d2541235c3308ddfb538
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e9dc835e73f838e73c433c4bc4e924ab
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_307f3ae33c0c53b5b839b0da66cc48b4
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_77cfde31570946bce80b65ac244cdae5
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bf8a734a36882d6133b6ba4ed6d3f2a6 |
| publicationDate |
2021-03-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
EP-3796370-A1 |
| titleOfInvention |
Contact over active gate structures with metal oxide layers to inhibit shorting |
| abstract |
Contact over active gate structure with metal oxide layers are described are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. A portion of one of the plurality of trench contact structures has a metal oxide layer thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on the metal oxide layer. |
| priorityDate |
2019-09-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |