| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_88fc7f9eb617072238851d46591a0c76 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N50-80
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B61-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B61-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N50-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-161
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N50-01 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-15
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L43-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L43-08 |
| filingDate |
2020-04-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ccbcd9fdf2a018693557873a243bea3c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f96b797b9c7051d1d9ec07bcc97ea8c3
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d6b75bcf4939a89341942ebec71bf3b3
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0c785e423c4f89d9dd5b23475f8e4457
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_90dcc31af1f105aeb57f94e4150eaf07
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0b9fc88a1f5167cd0c674573607225ac
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_008d7debbb0ecc9b82b99eadde1b962b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9adadb9bb136f94523171e6fb866e061
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c13aa3f79f2d9dad5fef54e5d66533d0
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e21bc81721a236ea6a37affc9bd5c71f |
| publicationDate |
2021-02-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
EP-3772117-A1 |
| titleOfInvention |
Semiconductor structure and method for forming the same |
| abstract |
A method for forming a semiconductor structure is disclosed. A substrate having a logic device region and a memory device region is provided. A first dielectric layer is formed on the substrate. Plural memory stack structures are formed on the first dielectric layer on the memory device region. An insulating layer is formed and conformally covers the memory stack structures and the first dielectric layer. An etching back process is performed to remove a portion of the insulating layer without exposing any portion of the memory stack structures. After the etching back process, a second dielectric layer is formed on the insulating layer and completely fills the spaces between the memory stack structures. |
| priorityDate |
2019-07-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |