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filingDate 2017-08-24-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bcda2a460e44ce374591abdbadce02be
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publicationDate 2019-07-31-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber EP-3516593-A1
titleOfInvention Programmable neuron core with on-chip learning and stochastic time step control
abstract An integrated circuit (IC), as a computation block of a neuromorphic system, includes a time step controller to activate a time step update signal for performing a time-multiplexed selection of a group of neuromorphic states to update. The IC includes a first circuitry to, responsive to detecting the time step update signal for a selected group of neuromorphic states: generate an outgoing data signal in response to determining that a first membrane potential of the selected group of neuromorphic states exceeds a threshold value, wherein the outgoing data signal includes an identifier that identifies the selected group of neuromorphic states and a memory address (wherein the memory address corresponds to a location in a memory block associated with the integrated circuit), and update a state of the selected group of neuromorphic states in response to generation of the outgoing data signal.
priorityDate 2016-09-26-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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