| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_bce787970b69aeb08d159e7c101c9ed7 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0245
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02502 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02381
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02461
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02463
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C23C8-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02532
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0262 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-203 |
| filingDate |
2016-07-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_01943bf60908e98a2ab7cdd233e222f6
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_10fe9f5edc441c18d86ba2b64dda197f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fc574a7ca258e5e3ab14044cf9e169b5
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7b8b693c0349d363884f14c1f852857e |
| publicationDate |
2018-06-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
EP-3332418-A1 |
| titleOfInvention |
Structure for relaxed sige buffers including method and apparatus for forming |
| abstract |
Embodiments of the present disclosures provide methods and apparatus for manufacturing semiconductor devices such as transistors used for amplifying or switching electronic signals. Specifically, embodiments of the present disclosure generally relate to a semiconductor device having a film stack including an interlayer of semiconductor material and a buffer layer of semiconductor material underneath an active device layer. In various embodiments, the interlayer may include group III-V semiconductor materials formed between a first surface of a silicon-based substrate and the buffer layer. In certain embodiments the buffer layer may comprise group IV semiconductor materials. The interlayer may have a lattice constant designed to mitigate lattice mismatch between the group IV buffer layer and the silicon-based substrate. The buffer layer may provide improved integration of the active device layer to improve the performance of the resulting device. |
| priorityDate |
2015-08-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |