| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_f56b5174f7d196258707ccf1d609796e |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-8238
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823871
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-84 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G05F1-625
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823481
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1203
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-7624
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6656
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41733
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42312
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-665
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K17-687
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0207
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1244
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-02 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-12 |
| filingDate |
2017-10-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cf97547e46b8a2bdbbaab6f43e6b80cc
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6a081e9055011b3eaf4acd36266d32c5 |
| publicationDate |
2018-08-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
EP-3321963-A3 |
| titleOfInvention |
Semiconductor device |
| abstract |
Reliability of a semiconductor device is improved. A p-type MISFET (Qp1) of a thin film SOI type is formed in an SOI substrate including a semiconductor substrate, an insulating layer (BX) on the semiconductor substrate, and a semiconductor layer (SM) on the insulating layer, and p + -type semiconductor regions (SDP) which are source and drain region of the p-type MISFET are formed in the semiconductor layer and an epitaxial layer (EP) on the semiconductor layer. A semiconductor layer (GN) is formed via the insulating layer below the p-type MISFET formed in the n-type well region (NW1) of the semiconductor substrate. In an n-type tap region (NTAP) which is a power supply region of the n-type well region, a silicide layer (SL) is formed on a main surface of the n-type well region without interposing the epitaxial layer therebetween. |
| priorityDate |
2016-11-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |