| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0e433c1625fc509a087c912b440da84b |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7811
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0653
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823418
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823456
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1095
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-266
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-063
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4238
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76232
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-407
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0878
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42368
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7809
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7813
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0882
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66734 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088 |
| filingDate |
2014-09-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_06eb1f14d2f9ad23d6e572597b222f06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_eef47fff808643c821a3608bd56715ba
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f03a5d4f4cba78bf3a6c1ad139d2cef2 |
| publicationDate |
2016-08-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
EP-3053193-A1 |
| titleOfInvention |
Vertical trench mosfet device in integrated power technologies |
| abstract |
In described examples, a semiconductor device (100) having a vertical drain extended MOS transistor (110) may be formed by forming deep trench structures (104) to define at least one vertical drift region (108) bounded on at least two opposite sides by the deep trench structures (104). The deep trench structures (104) include dielectric liners (124). The deep trench structures (104) are spaced to form RESURF regions for the drift region (108). Vertical gates (114) are formed in vertically oriented gate trenches in the dielectric liners (124) of the deep trench structures (104), abutting the vertical drift regions (108). A body implant mask for implanting dopants for the transistor body (118) is also used as an etch mask for forming the vertically oriented gate trenches in the dielectric liners (124). |
| priorityDate |
2013-10-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |