| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fbb16b39443f72f271c474607c90fced
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_4069895a5bad4014e19777722c5be042
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_37f4922dfb7777b019e504b885211b8e |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y02E10-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y02E10-545 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L31-02327
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L31-0392
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L31-0236
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L31-02363
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L31-02168
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L31-03685
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L31-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L31-1868
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L31-02366 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L31-0232
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L31-0236
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L31-0216 |
| filingDate |
2014-12-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_89e2185c27131305453ae0d8e428f108
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a6fcff244d53c2c7d3d1e5c1876cce8c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c99817edfe33e5acbfb59ee27973bd15
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2f2ad6652265cd6a4f3cda48f6ff76a0 |
| publicationDate |
2016-06-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
EP-3038164-A1 |
| titleOfInvention |
Opto-electronic device with textured surface and method of manufacturing thereof |
| abstract |
The present invention concerns an opto-electronic device comprising a semiconducting substrate, a layered interface comprising at least one layer (2, 3), said layered interface having a first surface (21) in contact with a surface (20) of said semiconducting substrate (1) and said layered interface being adapted for passivating said surface (20) of said semiconducting substrate (1), said layered interface having a second surface (23) and said layered interface being adapted for electrically insulating said first surface (21) from said second surface (23), and a textured surface structure comprising a plurality of nanowires (4) and a transparent dielectric coating (5), said textured surface structure being in contact with said second surface (23) of said layered interface, said plurality of nanowires (4) protruding from said second surface (23) and said plurality of nanowires (4) being embedded between said second surface (23) and said transparent dielectric coating (5). |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/NL-2020296-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2019143241-A1 |
| priorityDate |
2014-12-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |