patent/EP-2881982-A2

http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-2881982-A2

Outgoing Links

Predicate	Object
assignee	http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_bcb788ac2ea1a772ff0a53a49e5e2375
classificationCPCAdditional	http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-207 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2933-0016 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L33-32
classificationCPCInventive	http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L33-40 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3245 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-2003 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-8252 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32051 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32134 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L33-325 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-452
classificationIPCInventive	http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8252 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3213 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3205 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-45
filingDate	2014-10-16-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor	http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_87f942e223614a44158bd1187fa5bd7b http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_dcd1fe13c421ba9c668cbdc7a3006699 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_472d68bf150febbfd96ade3bad85848a http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3dbb4683f6eee684b17ad60ece5bf725
publicationDate	2015-06-10-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber	EP-2881982-A2
titleOfInvention	Method for fabricating cmos compatible contact layers in semiconductor devices
abstract	A method for fabricating Complementary Metal Oxide Semiconductor (CMOS) compatible contact layers in semiconductor devices is disclosed. In one embodiment, a nickel (Ni) layer is deposited on a p-type gallium nitride (GaN) layer of a GaN based structure. Further, the GaN based structure is thermally treated at a temperature range of 350°C to 500°C. Furthermore, the Ni layer is removed using an etchant. Additionally, a CMOS compatible contact layer is deposited on the p-type GaN layer, upon removal of the Ni layer.
priorityDate	2013-12-05-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type	http://data.epo.org/linked-data/def/patent/Publication

Incoming Links

Predicate	Subject
isDiscussedBy	http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID80922 http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID128361982

Total number of triples: 29.