| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_91fe1cddc99f9255118b5a663deed0fc |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-32225
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-32145
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-48227
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-73265
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-73257
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-16225
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-73204
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-181
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-15311 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/A61N1-36171
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/A61N1-05
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/A61N1-0534
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/A61N1-36125 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/A61N1-36 |
| filingDate |
2013-01-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f394052867a9817856953d107cf32bba
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c65079f85f3fb7cf392596f9cfa488f2
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f3a6b0d85078da87ae29cabfe72357c6
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fdab3687ea8e88a59aaed7abe307c0a0
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4d4279ee8175b17f6ffde7340594e67c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0fa9ee3ca9494178f0755c611658b3c1 |
| publicationDate |
2014-11-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
EP-2804664-A1 |
| titleOfInvention |
Architectures for an implantable stimulator device having a plurality of electrode driver integrated circuits with shorted electrode outputs |
| abstract |
Disclosed is a new architecture for an IPG having a master and slave electrode driver integrated circuits. The electrode outputs on the integrated circuits are wired together. Each integrated circuit can be programmed to provide pulses with different frequencies. Active timing channels in each of the master and slave integrated circuits are programmed to provide the desired pulses, while shadow timing channels in the master and slave are programmed with the timing data from the active timing channels in the other integrated circuit so that each chip knows when the other is providing a pulse, so that each chip can disable its recovery circuitry so as not to defeat those pulses. In the event of pulse overlap at a given electrode, the currents provided by each chip will add at the affected electrode. Compliance voltage generation is dictated by an algorithm to find an optimal compliance voltage even during periods when pulses are overlapping. |
| priorityDate |
2012-01-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |