http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-2588875-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_52cd439c9a2051257abb747c6db09c19 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-317 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-3177 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-318544 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-318558 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-318572 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-3185 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-3185 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-3177 |
| filingDate | 2011-06-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4c227baa46bcd6afe1e94b759dbf231e http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_718c7c235bab18995168deaf628a77c7 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c0bff22608a40499d813675e32e29482 |
| publicationDate | 2013-05-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | EP-2588875-A1 |
| titleOfInvention | Method and apparatus for virtual in-circuit emulation |
| abstract | A virtual In-Circuit Emulation (ICE) capability is provided herein for supporting testing of Joint Test Action Group (JTAG) hardware. A Virtual ICE Driver is configured for enabling any debug software to interface with target hardware in a flexible and scalable manner. The Virtual ICE Driver is configured such that the test instruction set used with the Virtual ICE Driver is not required to compute vectors, as the JTAG operations are expressed as local native instructions on scan segments, thereby enabling ICE resources to be accessed directly. The Virtual ICE Driver is configured such that ICE may be combined with instrument-based JTAG approaches (e.g., the IEEE P1687 standard and other suitable approaches). The Virtual ICE Driver is configured for receiving a plurality of scan segment operations generated by a plurality of target ICE controllers of at least one ICE host, scheduling the received scan segment operations, based at least in part on a scan chain of the target hardware, to form thereby a scheduled set of scan segment operations, and providing the scheduled set of scan segment operations to a processor configured for executing the scheduled set of scan segment operations for testing the target hardware. |
| priorityDate | 2010-06-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 305.