| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_986d0ab29fa7910a46cd21a12d682fe4 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66462
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7786
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-2003
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-513
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-518
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-291
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-3171
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7783
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-205
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7787 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-29
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-20 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-51
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-778 |
| filingDate |
2012-06-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3721ac9bf47519508e1216b14080055c |
| publicationDate |
2013-01-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
EP-2541605-A1 |
| titleOfInvention |
CMOS compatible method for manufacturing a HEMT device and the HEMT device thereof |
| abstract |
Method for manufacturing a III-nitride HEMT having a gate electrode and source and drain ohmic contacts comprising: providing a substrate; forming a stack of III-nitride layers on the substrate; forming a first passivation layer comprising silicon nitride overlying and in contact with an upper layer of the stack of III-nitride layers, wherein the first passivation layer is deposited in-situ with the stack of III-nitride layers; forming a dielectric layer overlying and in contact with the first passivation layer; forming a second passivation layer comprising silicon nitride overlying and in contact with the dielectric layer wherein the second passivation layer is deposited at a temperature higher than 450°C by LPCVD or MOCVD or any equivalent technique; and thereafter forming the source and drain ohmic contacts and the gate electrode. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-2930754-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11538908-B2 |
| priorityDate |
2011-06-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |