http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-2457150-A1

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http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03M7-3091
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F5-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03M7-46
filingDate 2010-07-20-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e1f22324678d7d724bfe2d7f345be1e3
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_020c67f83513ee5c89369ca24b59512d
publicationDate 2012-05-30-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber EP-2457150-A1
titleOfInvention Interfacing circuit comprising a fifo storage
abstract An interfacing circuit comprising a First In First Out (FIFO) memory for exchanging data between a "data producer device" and a "data consumer device". The FIFO memory is controlled by first write control signals (WR, CLK_WR) and second read control signals (ENABLE, Clk_Rd). The interfacing circuit further includes: a redundancy filter (230) for receiving a sequence of N data (Y 0 , Y 1 , Y 2 .... Y n-1 ) to be stored within said FIFO, and for generating a redundancy control word representative of the presence of consecutive identical data within said sequence; means (250) for controlling said first and said second control signals of said FIFO for the purpose of preventing the storage into said FIFO of multiple consecutive identical data and more important to make possible to accelerate the average speed of the data flux going to the "data consumer device" without need to accelerate the clocking of the memory feeding the said FIFO thanks to increase of efficiency of transfers due to redundancy filtering.
priorityDate 2009-07-21-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 20.