Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c3a2f00e72ba6e4c09b6da573427fbed |
classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2207-107 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-401 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1012 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-222 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-028 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1006 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-22 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1078 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1051 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1069 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1096 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1072 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4096 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-023 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-4096 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C5-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-401 |
filingDate |
2009-07-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fad9f4bac3903d5bc343229c3154dbad http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0cb0070f7452c8000414f933bedc89a8 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3a2afee464d39716762f2d285a611252 |
publicationDate |
2011-05-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
EP-2319044-A2 |
titleOfInvention |
Memory system and method using stacked memory device dice, and system using the memory system |
abstract |
A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time. |
priorityDate |
2008-07-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |