| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_38ed56a4b4e8e2315b2b3308bffedb3f |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0251
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C30B23-066
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C30B23-025
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C30B25-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C30B25-183
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02381
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0245
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02505
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823807
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0262
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C30B29-52
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02532 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L31-0328
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C30B25-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-205
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-302
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C30B29-52 |
| filingDate |
2003-08-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_886dd8cacd6a3d84cde5c94bfc2496b4
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0778de36c55d54a6756c00d302d76575
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9dc1acc0aad7d5b9a47756b1b1040a23
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_93d1af0a5ba3b5fd644815291ab2b9ae
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4686d8d979f0a99c85929d7fc17b1bc4 |
| publicationDate |
2010-12-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
EP-2267762-A2 |
| titleOfInvention |
Semiconductor heterostructures having reduced dislocation pile-ups and related methods |
| abstract |
Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein. |
| priorityDate |
2002-08-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |