| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_70a46a00321ea11325fae74ac5c3b9ba
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_bdad3a90eb8733d4223bb4920c6ae650
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_4a40105ca1d63e6a5a52f3cd79ad135a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_65b6508bf3ccf8dd17bcbdd680345006
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_48de9d5b95f5d06190085ac822d04b70
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_29c527e6ba6286c483cdbfd18a9399f5 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y02D10-00 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F15-17375
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1072
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0607 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L25-00 |
| filingDate |
2008-06-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c70f1da283694791fae43e481527e485
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7fd8724b04e3dacf430d82c8e1ebed5d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7acec7b78572e17d1cf30fcdee7af91e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3a1735ee2f738fe6894b57e4f456d99e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e405614d9a3c224d40556015906e392a |
| publicationDate |
2010-03-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
EP-2160762-A1 |
| titleOfInvention |
An interconnect implementing internal controls |
| abstract |
A method, apparatus, and system are described, which generally relate to an integrated circuit having an interconnect that implements internal controls. The interconnect may maintain transaction path order to support outstanding transactions to multiple targets while maintaining transaction ordering; maintain request path order; maintain response path order; interleave channels in an aggregate target with unconstrained burst sizes; have configurable parameters for channels in an aggregate target and mapping of address regions onto the one or more aggregate targets; chop individual transactions whose data address sequence within that transaction crosses an interleaved channel address boundary in an aggregate target; chop individual 2-Dimensional (2D) transactions that cross channel boundaries headed for channels in an aggregate target so that two or more of the chopped portions retain their 2D burst attributes, as well as implement many other internal controls. |
| priorityDate |
2007-06-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |