http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-2100334-A2

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filingDate 2007-12-26-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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publicationDate 2009-09-16-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber EP-2100334-A2
titleOfInvention Geometry of mos device with low on-resistance
abstract A Metal Oxide Semiconductor (MOS) device formed on a substrate and a method for forming the MOS device. The MOS device includes a drain region, a gate region surrounding the drain region, source regions arranged around the gate region and across from the drain region, and bulk regions arranged around the gate region and separating the source regions. The gate region is formed in a loop around the drain region. In this manner, the on-resistance (Ron) of a MOS device is decreased without also increasing the area of the MOS device.
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Total number of triples: 26.