| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6b822ee046eb6c45d1e3bd9ce9c1782e |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66772
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0696 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-2007
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78603
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66712
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-124
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1266
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7812
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76254 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06 |
| filingDate |
2008-12-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_21747acfb77b0d181ab4dff0d66658d4 |
| publicationDate |
2009-06-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
EP-2068366-A2 |
| titleOfInvention |
Semiconductor device and manufacturing method thereof |
| abstract |
A semiconductor device with increased freedom of wirings and a manufacturing method thereof are provided by enabling favorable connection between an upper wiring layer and a lower wiring layer through a semiconductor element. The semiconductor device includes: a first insulating layer (126) over an insulating substrate (100); a first wiring layer (118) and a second insulating layer (122) on the first insulating layer; a single crystal semiconductor layer (132) including a channel region and an impurity region, on the first wiring layer and the second insulating layer; a gate electrode over the channel region with a gate insulating layer interposed therebetween; a third insulating layer covering the first wiring layer, the single crystal semiconductor layer, and the gate electrode; and a second wiring layer over the third insulating layer. The first wiring layer is in contact with the impurity region, and the first and wiring layers are electrically connected to each other. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9978757-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2015213185-A |
| priorityDate |
2007-12-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |