http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-1987424-A2
Outgoing Links
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assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c05beffcff6957bb314d2c084bf8086e |
classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F7-49921 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2207-382 |
classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F7-57 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F7-505 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3885 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-30 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-30014 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F17-142 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-30036 |
classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-302 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-38 |
filingDate | 2007-01-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_da70eb47aacc36e081769c3f71f317ec http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_65be01c5bd0398de336309bd95d267d4 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_83ecb64704f19e60bcfa887ebd69adb8 |
publicationDate | 2008-11-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber | EP-1987424-A2 |
titleOfInvention | Packed add-subtract operation in a micrprocessor |
abstract | A packed half-word addition and subtraction operation is performed by a microprocessor in parallel upon half word operands obtained from designated top (_T) or bottom (_B) half-word locations of; designated source registers (REGA, REGB) of a register file (19) and the sum and difference results of such operation are packed into respective top and bottom half - word locations of a designated destination register (DST_REG). The microprocessor includes an arithmetic-logic unit (ALU 11) with adder circuitry that can be selectively split into separate half -word adders (13, 15) that are independently selectable (ADDSUB_CTL_T, ADDSUB_CTL_B) to perform -either an addition operation or subtraction operation upon the selected half-word operands (OP_B_T, OP_A_T, OP_B_B, OP_AB). The half word adders of the ALU access the operands from source registers via a set of multiplexers (21 - 26) that select among the top and bottom half-word locations. Operations with halving and saturation modifications to the sum and difference results may also be provided. |
priorityDate | 2006-02-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 29.