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publicationDate 2008-11-05-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber EP-1987424-A2
titleOfInvention Packed add-subtract operation in a micrprocessor
abstract A packed half-word addition and subtraction operation is performed by a microprocessor in parallel upon half word operands obtained from designated top (&lowbar;T) or bottom (&lowbar;B) half-word locations of; designated source registers (REGA, REGB) of a register file (19) and the sum and difference results of such operation are packed into respective top and bottom half - word locations of a designated destination register (DST&lowbar;REG). The microprocessor includes an arithmetic-logic unit (ALU 11) with adder circuitry that can be selectively split into separate half -word adders (13, 15) that are independently selectable (ADDSUB&lowbar;CTL&lowbar;T, ADDSUB&lowbar;CTL&lowbar;B) to perform -either an addition operation or subtraction operation upon the selected half-word operands (OP&lowbar;B&lowbar;T, OP&lowbar;A&lowbar;T, OP&lowbar;B&lowbar;B, OP&lowbar;AB). The half word adders of the ALU access the operands from source registers via a set of multiplexers (21 - 26) that select among the top and bottom half-word locations. Operations with halving and saturation modifications to the sum and difference results may also be provided.
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