http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-1898426-A2
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_8292741de96a44319670508be1f78f1a |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2013-0071 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2013-009 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2013-0078 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2213-79 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10S977-754 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0028 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0023 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0004 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0069 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-02 |
| filingDate | 2007-08-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f07612f1c606bfb8b1350e781c558d28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4e7c34a74bcfa4cf0b1578ecdad5fc72 |
| publicationDate | 2008-03-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | EP-1898426-A2 |
| titleOfInvention | Erasable phase-change memory, programmable using a line decoder |
| abstract | The invention relates to an integrated circuit comprising a non-volatile memory comprising memory cells (CEL) each comprising a memory point (P) and a selection transistor (TS) having a control terminal connected to a word line (WL). , a line decoder (RDEC) for providing word line selection (SWL) signals, and at least one generator (LTC) for supplying memory cells with an erase voltage (Vp) or an erase current (Ip) or programming. According to the invention word line drivers (DRV) are interposed between the line decoder and the word lines, and are arranged to apply to a word line selected by the line decoder control pulses (VPULSEi) whose the profile corresponds to a pulse profile of voltage or erase or programming current. Application in particular to phase change memories. |
| priorityDate | 2006-09-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 24.